Probability Formulation of Soft Error in Memory Circuit

Downscaling threatens the designers invested in integrity and error mitigation against soft errors. This study formulated probability of changing logic state a Differential Logic with an Inverter Latch (DIL). Using Cadence Virtuoso, current pulses were injected into various nodes stages until flip was instigated. The voltage temperature parameters increased to observe level changes over time. critical charge from each stage obtained, method formulate instance developed. produced higher effect change any as compared temperature. findings revealed that N-channel metal-oxide semiconductor (NMOS) drain is more vulnerable variation than P-channel (PMOS).